Jitter Optimization Using the Body Bias in Digital CMOS Ring Oscillators ( EE 241 Project , May 5 , 2003 )

— This paper investigates the concept of using body bias as a design tool to optimize the timing jitter and power dissipation in single ended CMOS ring oscillators. A theoretical model for phase noise and timing jitter in ring oscillators is summarized and used as a basis for simulation of the impulse sensitivity function. Simulation results are then used to estimate timing jitter and phase noise and a comparison is made with the theoretical prediction. It is shown that simulation results are in good agreement with theory and that body bias can allow ~10% power reduction in the ring oscillator with minimal effect on (to slightly improving) timing jitter.